As the demand for more powerful and flexible computing devices increases, more and more Systems-on-Chip (SoC) are being developed. Many SoCs comprise Application Specific Integrated Circuits (ASICs) that are offered by several companies.
The Advanced RISC Machines (ARM) microprocessor is very popular for SoC solutions. Today it is fair to say that the ARM Embedded Technology is universally recognised as an industry standard for ASIC design for portable applications. Creating and applying powerful, portable and at the same time re-usable Intelligent Property (IP), capable of enhancing an ARM core is therefore of utmost importance to any ASIC design centre.
AMBA is an open standard, on-chip bus specification that details a strategy for the interconnection and management of functional blocks that makes up a SoC. AMBA defines a signal protocol for the connection of multiple blocks in a SoC. It facilitates the development of embedded processors (e.g., ARM microprocessors) with multiple peripherals. AMBA enhances a reusable design methodology by defining a common bus structure for SoC modules.
SoCs, and in particular ARM-based SoCs, are well suited for communication applications, including cable modems, xDSL, Voice-over-IP (VoIP) and Internet appliances, handheld devices (e.g., Personal Digital Assistants), GSM and UMTS systems, digital video cameras, hand sets, and so forth. SoCs can also be used by the automotive industries., e.g. for handling tasks inside a car.
A typical AMBA-based SoC 10 consists of an AHB system bus 16 and peripheral bus 19, as illustrated in FIG. 1. An Advanced System Bus can be employed instead of the AHB. In many SoC implementations, an Advanced Peripheral Bus (APB) is employed as peripheral bus. The SoC 10 further comprises an ARM processor 11—such as a high-speed ARM7TDMI 32-Bit RISC Central Processing Unit (CPU)—an internal memory (e.g., a Random Access Memory) 12, an external memory interface 13, and a Direct Memory Access Unit (DMAU) 14. All these functional blocks are connected to the AHB 16. The peripheral bus 19 is connected via an APB bridge 15 to the AHB 16. In the present example, two peripherals (keyboard scanner 17 and UART 18) are connected to the peripheral bus 19. In known ARM-based SoC implementations, the functional blocks may be clocked by a common clock, e g., a HCLK clock in an AHB implementation and a BCLK clock in an ASB implementation. For this purpose, a clock line 20 is connected to the respective functional blocks, as illustrated in FIG. 1.
There are situations where it is necessary to drive the APB peripherals with a lower clock frequency than the functional blocks that are connected to the AHB or ASB bus. It is desirable, to provide for means that allow to reduce the power consumption of the SoC. There is no standardised solution to this problem. If somebody wants to run functional blocks in the APB domain at a lower clock speed than the AHB- or ASB domain's clock speed, and to reduce the power consumption, then a solution has to be developed from scratch. Since there is no standardised solution, the peripherals are not interchangeable.
A problem occurs if a functional block within the high clock frequency domain (i.e., within the AHB- or ASB-domain) transfers data to a functional block in the low clock frequency domain (e.g., within the APB domain). Since the functional block in the low clock frequency domain is not able to cope with the amount of data transmitted by the functional block in the high clock frequency domain, a congestion is likely to occur.